Conventional n-type doped polysilicon gate electrodes in CMOS technology have two problems. Firstly, the polysilicon is conductive but there can still be a surface region which can be depleted of carriers under bias conditions. This appears as an extra gate insulator thickness and is commonly referred to as gate depletion and contributes to the equivalent oxide thickness. While this region is thin, in the order of a few angstroms (Å), it becomes appreciable as gate oxide thicknesses are reduced below 2 nm or 20 Å. Another problem is that the work function is not optimum for both n-MOS and p-MOS devices, historically this was compensated for by threshold voltage adjustment implantations. However, as the devices become smaller, with channel lengths of less than 1000 Å and consequently surface space charge regions of less than 100 Å, it becomes more and more difficult to do these implantations. Threshold voltage control becomes an important consideration as power supplies are reduced to the range of one volt. Optimum threshold voltages for both PMOS and NMOS transistors need to have a magnitude of around 0.3 Volts.
A solution to the polysilicon gate depletion problem is to replace the semiconducting gate material with a metal or highly conductive metallic nitrides. (See generally; Y. Yee-Chia et al., “Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric IEEE Electron Device Letters, Volume: 22 Issue: 5, May, 2001, pp. 227229; L Qiang, Y. Yee Chia, et al., “Dual-metal gate technology for deep-submicron CMOS transistors,” VLSI Technology, 2000; Digest of Technical Papers. 2000 Symposium on, 2000, pp. 72-73.; and H. Wakabayashi et al., “A dual-metal gate CMOS technology using nitrogen-concentration-controlled TiNx film,” Electron Devices, IEEE Transactions on, Volume: 48 Issue: 10, Oct. 2001, Page(s): 2363-2369.).
As with any new circuit material, the gate electrode must be chemically and thermally compatible with both the transistor and the process. Different metals can be employed or the properties of the conductive nitride modified to provide an optimum work function. (See generally; above cited reference).
The work function of the gate electrode—the energy needed to extract an electron—must be compatible with the barrier height of the semiconductor material. For PMOS transistors, the required work function is about 5.0 eV. Achieving the lower work function needed by NMOS transistors, about 4.1 eV, has been more difficult. FIGS. 1A and 1B illustrate the desired energy band diagrams and work functions for NMOS and PMOS transistors respectively. Refractory metals like titanium (Ti) and tantalum (Ta) oxidize rapidly under typical process conditions. One proposed solution to the problem relies on a “tuned” ruthenium-tantalum (Ru—Ta) alloy, which is stable under process conditions. When the Ta concentration is below 20 percent, the alloy's electrical properties resemble Rhubidium (Ru), a good PMOS gate electrode. When the Ta concentration is between 40 percent and 54 percent, the alloy is a good NMOS gate electrode. (See generally; H. Zhong et al., “Properties of Ru—Ta Alloys as gate electrodes for NMOS and PMOS silicon devices,” Digest of IEEE Int. Electron Devices Meeting, Washington D.C., 2001, paper 20.05; V. Misra, H. Zhong et al., “Electrical properties of Ru-based alloy gate electrodes for dual metal gate Si-CMOS,” IEEE Electron Device Letters, Volume: 23 Issue: 6, Jun. 2002 Page(s): 354-356; and H. Zhong et al., “Electrical properties of RuO/sub 2/gate electrodes for dual metal gate Si-CMOS,” IEEE Electron Device Letters, Volume: 21 Issue: 12, Dec. 2000 Page(s): 593-595).
Promising candidates include metallic nitrides, such as tantalum nitride (TaN) and titanium nitride (TiN). Tantalum nitride, titanium nitride, and tungsten nitride are mid-gap work function metallic conductors commonly described for use in CMOS devices. (See generally, H. Shimada et al., “Low resistivity bcc-Ta/TaN/sub x/metal gate MNSFETs having plane gate structure featuring fully low-temperature processing below 450 degrees C.,” 2001 Symposium on VLSI Technology, 12-14 Jun. 2001, Kyoto, Japan Page: 67-68; H. Shimada et al., “Tantalum nitride metal gate FD-SOI CMOS FETs using low resistivity self-grown bcc-tantalum, layer,” IEEE Trans. on Electron Devices, vol. 48, no. 8, pp. 1619-26, August 2001; B. Claflin et al., “Investigation of the growth and chemical stability of composite metal gates on ultra-thin gate dielectrics,” MRS Symposium on Silicon Front-End Technology-Materials Processing and Modelling, 13-15 Apr., 1998, San Francisco, Calif., Page: 171-176; A. Yagishita et al., “Dynamic threshold voltage damascene metal gate MOSFET(DT-DMG-MOS) with low threshold voltage, high drive current and uniform electrical characteristics,” Digest Technical Papers Int. Electron Devices Meeting, San Francisco, December 2000, pp. 663-6; B. Claflin et al., “Investigation of the growth and chemical stability of composite metal gates on ultra-thin gate dielectrics,” MRS Symposium on Silicon Front-End Technology-Materials Processing and Modelling, 13-15 Apr., 1998, San Francisco, Calif., Page: 171-176; and M. Moriwaki et al., “Improved metal gate process by simultaneous gate-oxide nitridation during W/WN/sub x/gate formation,” Jpn. J. Appl. Phys., vol. 39. No. 4B, pp. 2177-80, 2000). The use of a mid-gap work finction makes the threshold voltages of NMOS and PMOS devices symmetrical in that the magnitudes of the threshold voltages will be the same, but both will have a magnitude larger than that which is optimum with low power supply voltages.
Recently physical deposition, evaporation, has been used to investigate the suitability of some ternary metallic nitrides for use as gate electrodes, these included TiAlN and TaSiN. (See generally, Dae-Gyu Park et al., “Robust ternary metal gate electrodes for dual gate CMOS devices,” Electron Devices Meeting, 2001. IEDM Technical Digest. International, 2001 Page(s): 30.6.1-30.6.4). However, these were deposited by physical deposition not atomic layer deposition and only capacitor structures were fabricated, not transistors with gate structures.
Thus, there is an ongoing need for improved CMOS transistor design.